Efficient measurement and optical proximity correction modeling to catch lithography pattern shift issues of arbitrarily distributed hole layer
With the continued shrinking of the critical dimensions (CDs) of wafer patterning, the requirements for modeling precision in optical proximity correction (OPC) increase accordingly. This requirement extends beyond CD controlling accuracy to include pattern alignment accuracy because misalignment can lead to considerable overlay and metal-via coverage issues at advanced nodes, affecting process window and yield. This paper proposes an efficient OPC modeling approach that prioritizes pattern-shift-related elements to tackle the issue accurately. Our method integrates careful measurement selection, the implementation of pattern-shift-aware structures in design, and the manipulation of the cost function during model tuning to establish a robust model. Confirmatory experiments are performed on a via layer fabricated using a negative tone development. Results demonstrate that pattern shifts can be constrained within a range of ?1 nm, remarkably better than the original range of ?3 nm. Furthermore, simulations reveal notable differences between post OPC and original masks when considering pattern shifts at locations sensitive to this phenomenon. Experimental validation confirms the accuracy of the proposed modeling approach, and a firm consistency is observed between the simulation results and experimental data obtained from actual design structures.
computational lithography、optical proximity correction、modeling、pattern shift、metrology
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2024-09-26（万方平台首次上网日期，不代表论文的发表时间）
共1页
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